# MICROPROCESSORS Multiple choice Questions & Answers

Posted On:February 5, 2019, Posted By: Latest Interview Questions, Views: 1685, Rating :     ## Best MICROPROCESSORS Objective Questions and Answers

Dear Readers, Welcome to MICROPROCESSORS Objective Questions have been designed specially to get you acquainted with the nature of questions you may encounter during your Job interview for the subject of MICROPROCESSORS MCQs. These Objective type MICROPROCESSORS Questions are very important for campus placement test and job interviews. As per my experience good interviewers hardly plan to ask any particular question during your Job interview and these model questions are asked in the online technical test and interview of many IT & Non IT Industries.

### 1. The minimum number of transistors required to implement a two input AND gate is

A. 2

B. 4

C. 6

D. 8

Answer: C A. NAND-NAND

B. OR-NAND

C. NAND-NOR

D. NOR-NAND

Answer: A

### 3. For a memory with a 16-bit address space, the addressability is

A. 16 bits

B. 8 bits

C. 2^16 bits

D. Cannot be determined

Answer: D

### 4. Because we wish to allow each ASCII code to occupy one location in memory, most memories are _____ addressable.

A. BYTE

B. NIBBLE

C. WORD (16 bits)

D. DOUBLEWORD (32 bits)

Answer: A

### 5. Circuit A is a 1-bit adder; circuit B is a 1 bit multiplier.

A. Circuit A has more gates than circuit B

B. Circuit B has more gates than circuit A

C. Circuit A has the same number of gates as circuit B

(Hint: Construct the truth table for the adder and the multiplier)

Answer: A

### 6. When the write enable input is not asserted, the gated D latch ______ its output.

A. can not change

B. clears

C. sets

D. complements

Answer: A

A. gate

B. mux

C. decoder

D. register

Answer: D

### 8. We say that a set of gates is logically complete if we can build any circuit without using any other kind of gates. Which of the following sets are logically complete

A. set of {AND,OR}

B. set of {EXOR, NOT}

C. set of {AND,OR,NOT}

D. None of the above

Answer: C

A. RS Latch

B. mux

C. nand

D. decoder

Answer: A

### 10. If the number of address bits in a memory is reduced by 2 and the addressability is doubled, the size of the memory (i.e., the number of bits stored in the memory)

A. doubles

B. remains unchanged

C. halves

D. increases by 2^(address bits)/addressability

Answer : C

A. m

B. 2^m

C. log2 (m)

D. 2*m

Answer: C

### 13. For the number A[15:0] = 0110110010001111, A[14:13] is ______ A[3:2].

A. less than

B. greater than

C. the same as

D . cannot be determined

Answer: C

### 14. Which of the following conditions is not allowed in an RS latch?

A. R is asserted, S is asserted

B. R is asserted, S is negated

C. R is negated, S is asserted

D. R is negated, S is negated

Answer: A

### 15. Which of the following pair of gates can form a latch?

A. a pair of cross coupled OR

B. a pair of cross copled AND

C. a pair of cross coupled NAND

D. a cross coupled NAND/OR

Answer: C

### 16. ‘Burst refresh’ in DRAM is also called

A. Concentrated refresh

B. Distributed refresh

C. Hidden refresh

D. None of the above

Answer: A

A. 2

B. 3

C. 4

D. 5

Answer: D

### 18. A real number consists of

A. integer part

B. integer part and fraction part

C. integer part, fraction part along with positive or negative sign

D. none of the above

Answer: C

### 19. Assertion (A): Negative values of incremental operator in DO loop are allowed in Fortran 77 but not in earlier versions of Fortran.

Reason (R): Fortran 77 has better array facilities than earlier versions of Fortran.

A. Both A and R are correct and R is correct explanation of A

B. Both A and R are correct but R is not correct explanation of A

C. A is correct R is wrong

D. A is wrong R is correct

Answer: B

A. 45 H

B. 6 AFH

C. 234

D. 64 H

Answer: C

A. True

B. False

Answer: B

### 22. An I/O processor controls the flow of information between

A. cache memory and I/O devices

B. main memory and I/O devices

C. two I/O devices

D. cache and main memory

Answer: B

A. True

B. False

Answer: A

### 24. When .9432 E – 4 is subtracted from .5452 E – 3 in normalized floating point mode

A. none of the numbers is changed

B. .9432 E – 4 is changed to .09432 E – 3 and .5452 E – 3 is not changed

C. .5452 E – 3 is changed to 5.452 E – 4 but .9432 E – 4 is not changed

D. both Ihe numbers are changed and their exponents are, made equal to -5

Answer: B

### 25. DS directive in 8085

A. forces the assembler to reserve one byte of memory

B. forces the assembler to reserve a specified number of bytes in the memory

C. forces the assembler to reserve a specified number of consecutive bytes in the memory

D. none of the above

Answer: C

A. 127

B. 127.0

C. 127

D. 125 + 3

Answer: A

### 27. The five flags in 8085 are designated as

A. Z, CY, S, P and AC

B. D, Z, S, P, AC

C. Z, C, S, P, AC

D. Z, CY, S, D, AC

Answer: A

A. Direct

B. Register

C. Implicit

D. Immediate

Answer: C

A. True

B. False

Answer: A

A. True

B. False

Answer: B

### 31. The timing difference between a slow memory and fast processor can be resolved if

A. processor is capable of waiting

B. external buffer is used

C. either (a) or (b)

D. neither (a) nor (b)

Answer: C

A. 1000

B. 10000

C. 100000

D. one million

Answer: D

A. True

B. False

Answer: B

### 34. Which of the following is not a general purpose peripheral?

A. I/O port

B. Programmable interrupt controller

C. Programmable CRT controller

D. Programmable interval timer

Answer: C

A. 1, 2, 3, 4

B. 1, 2, 4, 3

C. 2, 1, 3, 4

D. 2, 1, 4, 3

Answer: A

A. +0

B. -0

C. +1

D. -1

Answer: B

### 37. The operating modes of 8255 A are called

A. mode 0 and mode 1

B. mode 0, mode 1 and mode 2

C. mode 0 and mode 2

D. mode 0, mode 2 and mode 3

Answer: B

### 38. Which of the following is type declaration statement in C?

A. int bar

B. s = s + 1

C. king = horse + 1

D. prin = prin * prin

Answer: A

A. True

B. False

Answer: A

### 40. A 37 bit mantissa has an accuracy of

A. 6 decimal places

B. 8 decimal places

C. 10 decimal places

D. 11 decimal places

Answer: D

### 41. In a C expression using assignment operators, relational operators and arithmetic operators, the hierarchy of operations (in the absence of parenthesis) is

A. assignment, relational, arithmetic

B. relational, assignment, arithmetic

C. arithmetic, assignment, relational

D. arithmetic, relational, assignment

Answer: D

### 42. In 8085, the pins for SID and SOD are

A. 4 and 5 respectively

B. 5 and 4 respectively

C. 3 and 4 respectively

D. 4 and 3 respectively

Answer: B

### 43. Assertion (A): Each memory chip has its own address latch.

Reason (R): ALE signal comes out of microprocessor 8085 and goes to memory chip.

A. Both A and R are correct and R is correct explanation of A

B. Both A and R are correct but R is not correct explanation of A

C. A is correct R is wrong

D. A is wrong R is correct

Answer: D

A. True

B. False

Answer: A

### 45. In C the keywords are also called

A. special words

B. reserved words

C. class words

D. character words

Answer: B

A. True

B. False

Answer: B

### 47. Which memory has read operation, byte erase, byte write and chip erase?

A. RAM

B. UVEPROM

C. EEPROM

D. both (b) and (c)

Answer: C

### 48. The forms of IF statements in FORTRAN 77 are called

A. logical IF and Block IF

B. logical IF, block IF and arithmetic IF

C. logic IF, block IF, arithmetic IF and negate IF

D. logical IF and arithmetic IF

Answer: B

### 49. In 8085

A. P flag is set when the result has even parity

B. P flag is set when the result has odd parity

C. P flag is reset when the result has odd parity

D. P flag is reset when the result has even parity

Answer: A

### 50. If the sign bit of mantissa is 0 and the exponent is increased from a positive to a more negative number the result is

A. a larger floating point number

B. a smaller floating point number

C. either (a) or (b) depending on the actual number

D. a negative floating point number

Answer: A